Conventional standard cell library architecture of semiconductor integrated circuits (IC) primarily contain a logic cell layout based in a metal oxide semiconductor environment, in particular a complimentary metal oxide semiconductor (CMOS) environment. Cell library designers strive to maximise the packing density of the logic cells within the standard cell library. Logic cells are composed of transistors that are arranged into base patterns or gate arrays of different types of logical operations, and then fabricated into an application specific IC (ASIC) to perform a specific function. A conventional ASIC layout is typically defined by an array of logic cells arranged in adjacent rows. Such an array is not shown, however, an example of a logic cell 12 is shown in FIGS. 1A-B. The cell is depicted for illustrative purposes as a mask layout design representation that is bound by power and ground rails 3, 5. Such layout design representation is a well known symbolic representation of the physical layout of logic cells. Each logic cell defines a specific logic circuit. The active areas or components of the logic cell include negative-channel diffusion 4, positive-channel diffusion 2, and gate 6 layers. The components of the logic cells are wired internally with vias 8 and metal layer 7 to form simple logic (NMOS and PMOS) gates to perform Boolean and logic functions, for example INVERTER (or NOT) 12, AND, OR, NAND, NOR, XOR, XNOR, ADDERS, FLIP-FLOP, and the like. The general composition and construction of such semiconductor IC physical components are materials well known in the industry, for example gate layer may be polysilicon, and metal layers may be aluminum or copper.
The cell library is typically designed with computer aided design (CAD) applications. The cells and the transistors within the cells are usually interconnected or wired using CAD with a placement and routing tool, typically with at least two metal layers 5, 7 (M1,M2, . . . ). One metal layer is vertically aligned with respect to the components of the cell to form vias 8 to interconnect the components of the cell with another interconnect metal layer (M1,M2, . . . ), which is configured horizontally to distribute power and ground to all cells.
The interconnection layout characteristics include cell pitch 14, transistor pitch 15, and wire track routing pitch 24. Typically transistor pitch is fixed, and cell pitch varies. FIG. 2 shows an array of cells in conventional arrangement showing cell pitch 14 and transistor pitch 15 of an inverter 12, NOR 33 and NAND 31 gate, respectively. Cell pitch is typically a multiple of transistor pitch, for example, an inverter gate 12 as shown in FIGS. 1A-B may be arranged to have a cell pitch that is 2× the transistor pitch. In the design of the interconnection layout, integrated circuit design rules must be observed, for example, minimum width of transistor width, minimum width of metal tracks, minimum spacing between metal tracks, and the like.
In the design of conventional cell library architecture, a mismatch or sub-optimal layout may exist between transistor pitch and routing pitch. Transistor pitch and routing pitch typically have different optimal spacing layouts. Therefore when they are made the same, or aligned, one or the other becomes sub-optimal, and larger than minimum. The sub-optimal layout of conventional transistor/routing pitch may result in inefficient use of IC area impacting IC performance therefore, it is desirable to remove the inefficient layout between transistor and routing pitches. For example, in a practical configuration, the transistor pitch may be 0.36 μm whereas the wire routing pitch may be 0.30 μm. Attempts have been made to match the cell pitch with either the transistor pitch or the wiring pitch, as shown in FIGS. 1A-B.
In FIG. 1A, if the cell pitch 14 is resized to match the wire 22 routing pitch 24 (0.30 μm) as in this configuration 10, the transistor efficiency of the cell 12 is reduced as indicated by wasted transistor area 16. With a cell pitch 14 of 0.30 μm, the routing efficiency is maximised, but the cell 12 must be three grids wide, or 0.90 μm. This reduces transistor efficiency by approximately 20%, compared with the two grids at 0.72 μm width of the initial transistor pitch of 0.36 μm. In other words, since the initial transistor pitch 24 is 0.06 μm greater than the routing pitch, additional grids are required for excess area due to the mismatch.
Alternatively, in FIG. 1B, if the routing pitch 24 is resized to match the cell pitch 14 (0.36 μm) of the cell 12 in this configuration 20, then routing efficiency is reduced as shown by wasted routing area 26. An inverter cell 12, having a cell pitch equal to 2× transistor pitch, may be built at the minimum of 0.72 μm width given a transistor pitch of 0.36 μm, which is only two grids wide, however, the routing efficiency is reduced by 17%. In other words, since the initial routing pitch is less than the transistor pitch, for every resized routing pitch 24 there is 0.06 μm wasted routing area 26.
An associated problem occurs with the routing efficiency when a metal width or spacing greater than the minimum is required which is discussed with reference to FIG. 3. The minimum spacing 34 between metal tracks 22 is defined by integrated circuit design rules. Centre points 32 of adjacent metal tracks 22 are also shown in FIG. 3. Increasing the metal width or spacing is often required to alleviate detrimental conditions due to cross-talk induced delays or glitches, electromigration, sidewall coupling, coupling capacitance, resistance or the like.
FIG. 3 shows a grid 30 defining a conventional routing pitch with (a) conventional spacing, (b) increased spacing 36 to limit cross-talk, and (c) increased metal widths 38 to limit electromigration. In section (a) of FIG. 3, a wiring pitch of 0.30 μm is defined on the routing grid, and metal width and spacing is 0.15 μm.
Conventionally, when increased spacing is required for example to control or limit cross-talk, the router in placement and routing tools of the CAD system places the next adjacent wire on the next grid over as shown in section (b) of FIG. 3. More specifically, the next adjacent metal is placed on the second grid over for space increases of 1.01× and up to 3× of the minimum. This approach is clearly inefficient when a small increase, for example 1.5×, in spacing is required.
In section (c) of FIG. 3, metal width increase may be made from 1.01× to 5×, which results in adjacent metal routes onto the second grid. Similarly, this is inefficient if small increases, for example 1.5×, in width is required. Although with this configuration, a maximum increase of 3× minimum spacing, or 5× minimum width with 3×3 via arrays, is achievable, these limits are excessive and routing efficiency and cell packing density is jeopardised.
Often attempts to reduce the cross-talk by increasing spacing to 1.5×-2× or to avoid electromigration by increasing width to 3× or increasing the number of vias to 2×2, have resulted in a conventional architecture that is inefficient and wasteful with respect to IC area and cell packing density.
There is a need for efficient use of cell architecture interconnection to align transistor pitch and routing pitch to increase wire routing density and cell packing density without compromising transistor performance or wire routing efficiency.